Cadence Design Systems, Inc. announce hotfix version 016 for 16.60 release. This update includes some critical bug fixes.
Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.
This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.
A hot fix is a software maintenance package containing a small number of code fixes, designed to fix a sall number of critical problems. A hot fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack.
Each successive Fix Pack is comprehensive and contains the material from the earlier Fix Packs for that Release, as well as all Interim Fixes made available since the previous Fix Pack or full Release. In other words, when multiple Fix Packs are available, you would not need to apply Fix Pack 1 before applying Fix Pack 2.
DATE: 09-27-2013 HOTFIX VERSION: 016
CCRID PRODUCT PRODUCTLEVEL2 TITLE
548538 CAPTURE NETLIST_ALLEGRO Enhancement:Include mechanical parts in Allegro netlist
1076579 CAPTURE GENERAL Display value only if value exists
1083904 FSP GUI Need Filter in Change FPGA dialog to select desire FPGA from the long list.
1089313 ALLEGRO_EDITOR INTERFACES Allegro Export PDF requires similar setup options as DE-HDL Export PDF for layer visibility
1095728 ALLEGRO_EDITOR EDIT_ETCH Slide to grab adjacent elements when extend selection is enabled
1102698 SIG_INTEGRITY ASSIGN_TOPOLOGY ECset will map on single ended nets but fails when the two nets are define as a diff pair.
1104071 SIG_INTEGRITY REPORTS Shape Parasitic value changes for bottom shape for changes in top shape
1117731 FSP POWER_MAPPING Ability to sort in Power Regulator forms
1121539 FSP CONFIG_SETTINGS Cannot configure special FPGA pins (temperature diodes)
1122721 FSP MODEL_EDITOR Partial copy-paste overwrites the complete cell in XML Editor
1123238 FSP TERMINATIONS Report functionality for terminations defined in the complete design.
1123364 FSP GUI Clicking on column header should sort the column.
1123403 FSP EXTERNAL_PORTS Improper checkbox selection for їDo Not Connectї or їExternal Portї column
1125611 CONCEPT_HDL OTHER display unconnected pin in schematic pdf.
1129871 ALLEGRO_EDITOR INTERACTIV Wire Profile Editor can't read mcmmat.dat in working directory.
1133688 ALLEGRO_EDITOR GRAPHICS Enhancement request to enable 3D Viewer to show STEP model from .dra file.
1141747 ALLEGRO_EDITOR GRAPHICS 3D view dooesnot displays height if step_unsupported_prototype variable set
1142215 SIG_INTEGRITY SIMULATION PULSE_PARAM set on DiffPair wasn't used for designlink simulation.
1142798 ALLEGRO_EDITOR INTERFACES Step file output is incorrect in step viewer when composed of arcs and line.
1142894 FSP GUI Ability to RMB on a header and select `Hide Columnї
1142940 FSP EXTERNAL_PORTS Issue with checking/unchecking "Do not connect" and "External port" cells
1142949 CONCEPT_HDL SKILL Usage of "Preferences > License Settingsї in FSP
1143091 SIP_LAYOUT SYMB_EDIT_APPMOD symed: When AddPins is used to add pins to a co-design die, those pins are not output as bumps in the die abstract
1144371 CONCEPT_HDL COMP_BROWSER Component Browser search results are inaccurate
1145033 ALLEGRO_EDITOR PLACEMENT When aligning components with options in Placement mode displays no busy indicator
1145286 CONCEPT_HDL CORE Directive required for switching off the console
1145800 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl.
1147899 ALLEGRO_EDITOR SHAPE Autovoid two overlapping shapes that share the same net
1149996 ALLEGRO_EDITOR EDIT_ETCH Routing does not follow the ratsnest 'pin to pin'.
1150847 ALLEGRO_EDITOR INTERFACE_DESIGN Rename of DiffPair was not retained.
1152577 ALLEGRO_EDITOR DATABASE slide removes cline seg
1152751 CONCEPT_HDL CORE Option to double-click and copy the Netname
1153220 ALLEGRO_EDITOR INTERFACES ENH: option to supress header/footer during PDF Export
1153625 ALLEGRO_EDITOR INTERFACES If Symbol has place bound bottom, the step model shows incorrect placement.
1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
1153857 CONCEPT_HDL CORE Changing different power symbol should maintain the schematic level properties.
1155161 CONCEPT_HDL CORE Add Signal name: Suggestion box overlaps with the typed signal name that is typed
1155922 CONCEPT_HDL OTHER How can I use the batch mode for PDF Publisher and print a variant overlay?
1156858 ALLEGRO_EDITOR PADS_IN PADS Translator: Missing drill on square PTH padstack
1157362 APD 3D_VIEWER Need a way to color multiple nets in 3D viewer from APD/SiP.
1158130 CONSTRAINT_MGR ANALYSIS Constraint Manager do not display the Cumulative Result in Reflection Simulation
1158210 ALLEGRO_EDITOR SHAPE SIP Layout happens crash while users move the shape with route keep-out
1158452 SIG_INTEGRITY GEOMETRY_EXTRACT CPW differential traces are not extracted as coupled when they are routed at an angle
1158827 ALLEGRO_EDITOR EDIT_ETCH Slide a via in pad automatically add cline back to via to pin.
1158871 PCB_LIBRARIAN IMPORT_CSV PIN TEXT is not automatically added when importing the .csv file
1159738 ALLEGRO_EDITOR INTERACTIV Selecting the Cancel button in the Text Edit command does not cancel the text.
1159878 SIG_EXPLORER OTHER Ecset mapping dont follow topology template
1159971 ALLEGRO_EDITOR MANUFACT Allegro PDF Publisher requires ability to control film record sequence when generating the combined PDF file
1160017 SIP_LAYOUT DIE_ABSTRACT_IF Add text to clarify shrink operation
1160507 APD EDIT_ETCH Script not playing back what was recorded when sliding lines
1161261 ADW TDO-SHAREPOINT Schema for TDO-SP fails on Japanese OS
1161538 CONCEPT_HDL CORE Espice model value edited in DE HDL & then netlisting done, but it doesnt changes the earlier assigned model in Allegro
1161636 ALLEGRO_EDITOR DRAFTING need new function for PDFout : hatching shape
1161777 ALLEGRO_EDITOR OTHER default line width for PDF output
1162383 CONCEPT_HDL CHECKPLUS Checkplus not using $CDS_SITE/custom_help and $CDS_SITE/custom_rules_include directories.
1162562 CAPTURE STABILITY Capture crash on second attempt of pspice netlist creation in 16.6
1162629 FSP PROCESS "Load Process Option" under Run does not work properly
1162686 CONCEPT_HDL CORE Changing NET_SPACING_TYPE to display both shows up with $NET_SPACING_TYPE
1163149 ALLEGRO_EDITOR DATABASE Autosilk creates Illegal arc to corrupt database
1163439 ALLEGRO_EDITOR COLOR Duplicate Views Listed in Visibility Tab.
1163521 CONCEPT_HDL COMP_BROWSER System Architect crahes on replace
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
1163902 APD EXPORT_DATA Q- In APD > File - Export - Board Level Component, check otion of delay reports is not working, is it ?
1164337 CONCEPT_HDL CORE Cannot delete attribute filter value in PDF > General > Attribute Filter list
1164365 ALLEGRO_EDITOR INTERACTIV Symbol not selected for Move because Symbol Pin number selected in options tab not available on symbol
1164769 APD VIA_STRUCTURE The replace via structure command does not accept a single canvas pick.
1165026 ASI_SI GUI EMS3D exist in Via Model Setup of SI base.
1165561 CAPTURE DRC File > Check and Save clears waived DRCs
1165631 CAPTURE STABILITY Capture crash in the hierarchy tab of Project Manager window
1165836 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.(update)
1165911 FSP PROCESS Editing group name in protocol causes incorrect Process option checked
1166026 ALLEGRO_EDITOR DATABASE Running DB Doctor removes net name from vias
1166034 SIP_LAYOUT OTHER SiP - Cline Change Width command enhanced to have selection by polygon not just rectangle
1166074 GRE CORE GRE crashes during planning phases
1166319 ALLEGRO_EDITOR PLACEMENT Swap not succeed
1166484 SIP_LAYOUT WIREBOND Bondfinger "Align With Wire" problem during move
1166530 ALLEGRO_EDITOR INTERACTIV Bug: Mirror in Placement Edit resets the options tab for Edit > Move
1166819 CONCEPT_HDL CORE Cadence DEHDL Text Size Issue
1167847 CAPTURE PROPERTY_EDITOR Implementation name length greater than 31 character causes capture crash
1167887 F2B OTHER Improve message on symbol to schematic generation
1168369 F2B DESIGNVARI Variant donїt appear in increasing order while Annotate.
1168629 APD OTHER Do we have Skill command which is equivilant to Change Characteristics operation of a Wire Bond in APD
1168678 ALLEGRO_EDITOR NC Drill Figure will be changed wrong layer when some subclass was deleted in SPB165S045.
1168798 ALLEGRO_EDITOR INTERACTIV Enh - Allow user the ability to set the visibiity layer of refdes while moving the symbol rather than fixing it to silk
1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
1168864 ALLEGRO_EDITOR CREATE_SYM Saving the dra after Shape Expand/Contract throws warning 'Sector Table is not empty
1169213 PSPICE SIMULATOR Parametric sweep is giving incorrect reuslts
1169436 FSP FPGA_SUPPORT Add support for Cyclone V CSX and CST parts
1170108 ALLEGRO_EDITOR INTERACTIV Enhancement to preserve Rat T location for Topology assigned schedule
1170313 SIP_LAYOUT LOGIC scm adding additional pin names and unassigned property to codesign die chips file
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
1171747 ALLEGRO_EDITOR PLACEMENT Allegro crashes when doing a gate swap between components
1172183 ALLEGRO_EDITOR INTERACTIV Alignment modules fails on equal spacing
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
1174067 ALLEGRO_EDITOR DRC_CONSTR Soldermask to shape drc does not show if the layer is a PLANE.
1174338 ALLEGRO_EDITOR PLACEMENT preview has rotated pads
1175307 CONSTRAINT_MGR ANALYSIS CMGR fails to report RPD DRC for accuracy 4 - mm
1175537 ALLEGRO_EDITOR REPORTS net loop report crashes Allegro. Design specific
1176126 ALLEGRO_EDITOR INTERFACES 3D viewer doesnot change models units dynamically
1176281 CONCEPT_HDL CORE Option to Auto-hide excluded modules
1176413 ALLEGRO_EDITOR MANUFACT Q - testprep parameter settings is not retained, what could be the cause..
1176791 ALLEGRO_EDITOR GRAPHICS Spurious odd lines are shown in shapes and text that are not part of the design with opengl
1178052 ALLEGRO_EDITOR SHAPE SIP crashes during shape degassing.
1178158 ALLEGRO_EDITOR INTERFACES Export step file creates step file of same height
1178201 ALLEGRO_EDITOR GRAPHICS Large oval pads rendered as oblong hexagons in the 3D viewer
1178671 ALLEGRO_EDITOR GRAPHICS 3D Viewer in package symbol editor not displaying correct place bound shapes.
1178725 ALLEGRO_EDITOR OTHER With fillets present, rat lines do not point to the closest endpoint.
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.
1179093 ALLEGRO_EDITOR SHAPE Dynamic Shape for GROUND net on TOP Layer is corrupted and is not voiding correctly in certain areas.
1179109 ALLEGRO_EDITOR OTHER DXF importing makes figure shift in 16.5&16.6 version it is ok in 16.3 version
1179571 ALLEGRO_EDITOR ARTWORK Artwork crash and artwork log report Aparture missing
1179636 SPECCTRA ROUTE Route Automatic will not start if NET_SHORT are attached to a mec-pin
1179659 SIP_LAYOUT DIE_EDITOR die edit on co-design die losing c4 bumps
1180306 ALLEGRO_EDITOR ARTWORK When trying to create Artwork the tool crashes with no error messages just a little X box
1180573 ALLEGRO_EDITOR ARTWORK If one layer has warning, all artwork films are "created with warning".
1180960 SIP_LAYOUT PLACEMENT swap function is not swapping logical paths in sip layout!
1182534 ALLEGRO_EDITOR SKILL axlLayerPrioritySet() not working with v166 s013 and up
1182560 ALLEGRO_EDITOR PLOTTING Creating plot 2nd time casues Allegro to crash
1182616 ALLEGRO_EDITOR PLACEMENT Application crashes when attempting to place a high pin count BGA
1183752 CONCEPT_HDL CORE Unable to modify location properties within a read-only hierarchical block
1183774 SIP_LAYOUT DIE_EDITOR Die Refresh hangs
1184178 CONCEPT_HDL CONSTRAINT_MGR Ecset xnet members lost from electrical class when restore from definition of subblocks
1184787 ALLEGRO_EDITOR EDIT_ETCH Allegro SPB166 s 015 crashes during normal add connect function.
About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.
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