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9-09-2013, 11:46

Cadence SPB OrCAD 16 50 047 Hotfix

Category: Software

Cadence SPB OrCAD 16 50 047 Hotfix

Cadence SPB OrCAD 16.50.047 Hotfix | 667.2 mb

Cadence Design Systems, Inc. announce hotfix version 047 for 16.50 release. This update includes some critical bug fixes.
New technologies in Allegro and OrCAD 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.

DATE: 09-6-2013 HOTFIX VERSION: 047

1095533 CONCEPT_HDL CORE changing visibility for $PNN results in crash in windows mode
1153813 CONCEPT_HDL CORE Spaces should not be allowed in the signal name entry form
1156102 PCB_LIBRARIAN CORE PDV severe performance degradation on Linux platform makes PDV counter productive after some time
1161781 CONSTRAINT_MGR CONCEPT_HDL SigXp crash when selecting ECset in design
1163709 CONCEPT_HDL CONSTRAINT_MGR Loosing Diffpairs when reimport block or restore from definitioin
1167887 F2B OTHER Improve message on symbol to schematic generation
1168496 ALLEGRO_EDITOR SCHEM_FTB Export Physical Crashes when netreving the board
1168830 ALLEGRO_EDITOR DRC_CONSTR missing DRC-marker for package to package check
1169593 CONCEPT_HDL PDF Published PDF file's hyperlinks do not work fine when user click 1D10 or 2A10.
1169984 F2B PACKAGERXL Error Mapping cset when packaging but not in CM Audit
1171136 CONCEPT_HDL CORE Page Number should also be displayed in Import Design Window.
1172597 ALLEGRO_EDITOR DATABASE Board cannot be unlocked using Password used while locking
1172938 ALLEGRO_EDITOR PLOTTING Export IPF probrem
1173183 ALLEGRO_EDITOR DRC_CONSTR Undesired Same net DRC for overlapping Pin and Via
1173829 ALLEGRO_EDITOR MANUFACT Backdrill completes even though a stub exceeds the MAX_PTH_STUB value
1178972 CONSTRAINT_MGR ANALYSIS The Cross-Section's parameters was not applied immediately after importing a DCF on the Constraint Manager.

A hot fix is a software maintenance package containing a small number of code fixes, designed to fix a small number of critical problems. A hot fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack.

Each successive Fix Pack is comprehensive and contains the material from the earlier Fix Packs for that Release, as well as all Interim Fixes made available since the previous Fix Pack or full Release. In other words, when multiple Fix Packs are available, you would not need to apply Fix Pack 1 before applying Fix Pack 2.

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.



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